1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to voltage generating circuits of a semiconductor memory device that are responsive to an operating mode.
2. Description of the Related Art
Recent technologies for fabricating semiconductor memory devices have become increasingly hyperfine and highly integrated. Thus, semiconductor memory devices having low power consumption are required. To reduce the power consumption, a power supply voltage to be applied to the semiconductor memory devices may be lowered.
Thus, a conventional semiconductor memory device includes an internal voltage generating circuit for supplying a power supply voltage from an external circuit using a power supply voltage of about 5 V to an internal circuit using a low power supply voltage of about 3.3 V. The internal voltage generating circuit generates an internal voltage in response to a reference voltage received from a reference voltage generating circuit.
In conventional semiconductor memory devices, operating modes are classified according to frequency range. Such operating modes are explained in relation to column address strobe (“CAS”) latency. The CAS latency (“CL”) is a time required for outputting data after a read command is input. That is, when a read command is input at a certain point of a clock signal and then data is output two cycles of the clock signal later, the operating mode is defined for a CAS latency of 2, and becomes, namely, “CL2”.
When a read command is input at a certain point of the clock signal and then data is output three cycles of the clock signal later, the operating mode becomes CL3. Likewise, when a read command is input at a certain point of the clock signal and then data is output two and a half cycles of the clock signal later, the operating mode becomes CL2.5.
If a semiconductor memory device is in the operating frequency range of about 100 to 133 MHz, the device operates in CL2 mode. If a semiconductor memory device is in the operating frequency range of about 166 to 200 MHz, the device operates in CL3 mode.
However, in conventional semiconductor memory devices, an internal voltage is maintained at a constant level regardless of the operating mode, or CL. Thus, when the semiconductor memory device is in an operating mode of a relatively low frequency range, it suffers from unnecessarily increased power dissipation.
Also, even if the internal voltage level of the semiconductor memory device is lowered in order to reduce the power dissipation, operating characteristics may be degraded in an operating mode of a higher frequency range, for example.
Thus, with conventional semiconductor memory devices, if an internal voltage level is controlled in order to improve the operating characteristics of a semiconductor memory device in a certain operating mode, the device may suffer from unnecessarily increased power dissipation in other operating modes.